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MC9S08SH8MFKRR Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc |
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MC9S08SH8MFKRR Datasheet(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 338 page  Chapter 1 Device Overview MC9S08SH8 MCU Series Data Sheet, Rev. 3 22 Freescale Semiconductor 1.3 System Clock Distribution Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following defines the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of ICSOUT. • ICSOUT — Primary output of the ICS and is twice the bus frequency. • ICSLCLK — Development tools can select this clock source to speed up BDC communications in systems where the bus clock is configured to run at a very slow frequency. • ICSERCLK — External reference clock can be selected as the RTC clock source and as the alternate clock for the ADC module. • ICSIRCLK — Internal reference clock can be selected as the RTC clock source. • ICSFFCLK — Fixed frequency clock can be selected as clock source for the TPM1, TPM2 and MTIM modules. • LPOCLK — Independent 1-kHz clock source that can be selected as the clock source for the COP and RTC modules. • TCLK — External input clock source for TPM1, TPM2 and MTIM and is referenced as TPMCLK in TPM chapters. Figure 1-2. System Clock Distribution Diagram TPM1 TPM2 MTIM SCI BDC CPU ADC IIC FLASH ICS ICSOUT ÷2 BUSCLK ICSLCLK ICSERCLK COP * The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. FLASH has frequency requirements for program and erase operation. See the electricals appendix for details. ADC has min and max frequency requirements. See the ADC chapter and electricals appendix for details. XOSC EXTAL XTAL SPI FFCLK* ICSFFCLK RTC 1 kHZ LPO TCLK ICSIRCLK ÷2 SYNC* LPOCLK |
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