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MC9S08SH4 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc |
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MC9S08SH4 Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 338 page  Chapter 2 Pins and Connections MC9S08SH8 MCU Series Data Sheet, Rev. 3 Freescale Semiconductor 29 Pin Number Priority 24-pin 20-pin 16-pin 8-pin Port Pin Alt 1 Alt 2 Alt 3 Alt 4 Alt5 1333 VDD 2— — — 3444 VSS 4 5 5 — PTB7 SCL1 1 IIC pins can be repositioned using IICPS in SOPT2, default reset locations are on PTA2 and PTA3. EXTAL 5 6 6 — PTB6 SDA1 XTAL 6 7 7 — PTB5 TPM1CH12 2 TPM1CHx pins can be repositioned using TPM1PS in SOPT2, default reset locations are on PTA0 and PTB5. SS PTC03 3 This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority over all digital modules. The output data, drive strength and slew-rate control of this port pin will follow the configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out. Ganged output not available in 8-pin packages. 7 8 8 — PTB4 TPM2CH1 MISO PTC03 8 9 — — PTC3 PTC03 ADP11 9 10 — — PTC2 PTC03 ADP10 10 11 — — PTC1 TPM1CH12 PTC03 ADP9 11 12 — — PTC0 TPM1CH02 PTC03 ADP8 12 13 9 — PTB3 PIB3 MOSI PTC03 ADP7 13 14 10 — PTB2 PIB2 SPSCK PTC03 ADP6 14 15 11 — PTB1 PIB1 TxD ADP5 15 16 12 — PTB0 PIB0 RxD ADP4 16 17 13 5 PTA3 PIA3 SCL1 ADP3 17 18 14 6 PTA2 PIA2 SDA1 ADP2 18 19 15 7 PTA1 PIA1 TPM2CH0 ADP14 4 If ACMP and ADC are both enabled, both will have access to the pin. ACMP–4 19 20 16 8 PTA0 PIA0 TPM1CH02 ADP04 ACMP+4 20 — — — 21 — — — 22 — — — 23 1 1 1 PTA55 IRQ TCLK RESET 24 2 2 2 PTA4 ACMPO BKGD MS 5 Pin is open-drain when configured as output driving high. Pin does not contain a clamp diode to V DD and should not be driven above VDD. The voltage measured on the internally pulled up RESET will not be pulled to VDD. The internal gates connected to this pin are pulled to VDD. Lowest Highest Table 2-1. Pin Availability by Package Pin-Count |
Similar Part No. - MC9S08SH4 |
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Similar Description - MC9S08SH4 |
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