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STM8S105C4T6CTR Datasheet(PDF) 11 Page - STMicroelectronics |
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STM8S105C4T6CTR Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 127 page Block diagram 3 Figure 1: STM8S105xx access line block diagram XTAL 1-16 MHz RC int. 16 MHz RC int. 128 kHz STM8 core Debug/SWIM I 2 C SPI UART2 16-bit general purpose AWU timer Reset block Reset POR BOR Clock controller Detector Clock to peripherals and core 8 Mbit/s Up to 10 channels Window WDG Independent WDG Up to 32 Kbytes 1 Kbytes Up to 2 Kbytes Boot ROM ADC1 Reset 400 Kbit/s Single wire debug interf. program Flash 16-bit advanced control timer (TIM1) timers (TIM2, TIM3) 8-bit basic timer (TIM4) data EEPROM RAM Master/slave autosynchro LIN master SPI emul. Beeper 1/2/4 kHz beep 5 CAPCOM channels Up to 4 CAPCOM channels +3 Up to complementary outputs 11/127 DocID14771 Rev 9 Block diagram STM8S105xx |
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