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XC6118C08CGR-G Datasheet(PDF) 6 Page - Torex Semiconductor |
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XC6118C08CGR-G Datasheet(HTML) 6 Page - Torex Semiconductor |
6 / 20 page 6/20 XC6118 Series PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CIRCUITS Operating Voltage VIN VDF(T)=0.8~5.0V (*1) 1.0 6.0 V - Detect Voltage VDF VIN=1.0~6.0V E-1 V ① Hysteresis Width VHYS VIN=1.0~6.0V E-3 V ① Detect Voltage Line Regulation ΔV DF/ (ΔVIN・VDF) VIN=1.0~6.0V ±0.1 %/V ① Supply Current 1 (*2) ISS1 VSEN=VDF×0.9 VIN=1.0V VIN=6.0V 0.4 0.4 1.0 1.0 μA ② Supply Current 2 (*2) ISS2 VSEN=VDF×1.1 VIN=1.0V VIN=6.0V 0.8 0.9 1.6 1.8 μA ② IOUT1 VSEN=0V VDS=0.5V(Nch) VIN=1.0V VIN=2.0V VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 mA ③ Output Current (*3) IOUT2 VSEN=6.0V VDS=0.5V(Pch) VIN=1.0V VIN=6.0V -0.30 -1.00 -0.08 -0.70 mA ④ CMOS Output 0.20 Leakage Current N-ch Open Drain Output ILEAK VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open 0.20 0.40 μA ③ Temperature Characteristics ΔV DF/ (ΔTopr・VDF) -40 oC≦T a≦85 oC ±100 ppm/ oC ① Sense Resistance (*4) RSEN VSEN=5.0V VIN=0V E-4 MΩ ⑤ Delay Resistance (*5) RDELAY VSEN=6.0V VIN=5.0V Cd=0V 1.6 2.0 2.4 MΩ ⑥ Delay capacitance pin Sink Current ICD Cd=0.5V, VIN=1.0V 200 μA ⑥ Delay Capacitance Pin Threshold Voltage VTCD VSEN=6.0V VIN=1.0V VSEN=6.0V VIN=6.0V 0.4 2.9 0.5 3.0 0.6 3.1 V ⑦ Undefined Operation (*6) VUNS VIN=VSEN=0~1.0V 0.3 0.4 V ⑧ Detect Delay Time (*7) tDF0 VIN=6.0V, VSEN=6.0→0V Cd: Open 30 230 μs ⑨ Release Delay Time (*8) tDR0 VIN=6.0V, VSEN=0→6.0V Cd: Open 30 200 μs ⑨ ■ELECTRICAL CHARACTERISTICS (Continued) ●XC6118xxxB Ta=25℃ NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: It is calculated from the voltage value of the VIN and the current value of the Cd. *6: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *7: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *8: Delay time from the time of VIN= VDF +VHYS to the time of VOUT= 5.4V when the VSEN rises. |
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