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XC6118 Datasheet(PDF) 12 Page - Torex Semiconductor

Part No. XC6118
Description  Voltage Detector with Separated Sense Pin & Delay Capacitor Pin
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Maker  TOREX [Torex Semiconductor]
Homepage  http://www.torex.co.jp
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XC6118 Datasheet(HTML) 12 Page - Torex Semiconductor

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XC6118 Series
When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for
the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay
resistor (Rdelay).
The inverter (Inv.1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic
Threshold: VTHL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF).
While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series
circuit.
Assuming the time to the release delay time (t
DR), it can be given by the formula (1).
tDR=-Rdelay×Cd×ln(1-VTCD/VIN) …(1)
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin voltage is VIN /2 (TYP.)
tDR=Rdelay×Cd×0.69 …(2)
*:Rdelay is 2.0MΩ(TYP.)
As an example, presuming that the delay capacitance is 0.68μF, t
DR is :
2.0×10
6×0.68×10-6×0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the ground
(=VSS) level because time described in ③ is short.
When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), the inverter
(Inv.1) will be inverted.
As a result, the output voltage changes into the “High” (=VIN) level.
t
DR0 is defined as time which
ranges from VSEN=VDF+VHYS to the VOUT of “High” level without connecting to the Cd.
While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the delay
capacitance pin voltage becomes the input voltage level.
Therefore, the output voltage maintains the “High”(=VIN) level.
●Function Chart
TRANSITION OF VOUT CONDITION *1
VSEN
Cd
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
●Release Delay Time Chart
DELAY
CAPACITANCE [Cd]
(μF)
RELEASE DELAY TIME [tDR]
(TYP.)
(ms)
RELEASE DELAY TIME [tDR] *2
(MIN. ~ MAX.)
(ms)
0.010
13.8
11.0 ~ 16.6
0.022
30.4
24.3 ~ 36.4
0.047
64.9
51.9 ~ 77.8
0.100
138
110 ~ 166
0.220
304
243 ~ 364
0.470
649
519 ~ 778
1.000
1380
1100 ~ 1660
*1: VOUT transits from condition ① to ② because of the combination of VSEN and Cd.
●Example
ex. 1) VOUT ranges from ‘L’ to ‘H’ in case of VSEN = ‘H’ (VDR≧VSEN), Cd=’H’ (VTCD≧Cd) while VOUT is ‘L’.
ex. 2) VOUT maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, VSEN=’H’ and Cd=’L’ when VOUT becomes ‘H’ in ex.1.
■OPERATIONAL EXPLANATION (Continued)
* The release delay time values above are calculated by using the formula (2).
*2: The release delay time (tDR) is influenced by the delay capacitance Cd.


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