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P89LPC915FN Datasheet(PDF) 11 Page - NXP Semiconductors |
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P89LPC915FN Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 75 page P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 15 December 2009 11 of 75 NXP Semiconductors P89LPC915/916/917 8-bit microcontrollers with accelerated two-clock 80C51 core 7.2 Pin description Table 4. P89LPC915 pin description Symbol Pin Type Description P0.0 to P0.5 I/O Port 0: Port 0 is a 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/KBI0 2 I/O P0.0 — Port 0 bit 0. O CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0. P0.1/CIN2B/KBI1/AD10 1 I/O P0.1 — Port 0 bit 1. I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD10 — ADC1 channel 0 analog input. P0.2/CIN2A/KBI2/AD11 14 I/O P0.2 — Port 0 bit 2. I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD11 — ADC1 channel 1 analog input. P0.3/CIN1B/KBI3/AD12 13 I/O P0.3 — Port 0 bit 3. I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD12 — ADC1 channel 2 analog input. P0.4/CIN1A/KBI4/AD13/ DAC1 12 I/O P0.4 — Port 0 bit 4. I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD13 — ADC1 channel 3 analog input. I DAC1 — DAC1 analog output. P0.5/CMPREF/KBI5/CLKIN 11 I/O P0.5 — Port 0 bit 5. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. I CLKIN — External clock input. P1.0 to P1.5 I/O, I [1] Port 1: Port 1 is a 6-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.13.1 “Port configurations” and Table 15 “Static characteristics” for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: |
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