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P89LPC914 Datasheet(PDF) 41 Page - NXP Semiconductors |
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P89LPC914 Datasheet(HTML) 41 Page - NXP Semiconductors |
41 / 66 page P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 28 September 2007 41 of 66 NXP Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core 8.18.7 Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device. 8.18.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0). 8.18.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3) Unlike the conventional UART, in double buffering mode, the TX interrupt is generated when the double buffer is ready to receive new data. 8.18.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3) If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TX interrupt. If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. 8.19 Serial Peripheral Interface (SPI) P89LPC912/913/914 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in Master mode or 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection. |
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