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STMPE811 Datasheet(PDF) 16 Page - STMicroelectronics |
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STMPE811 Datasheet(HTML) 16 Page - STMicroelectronics |
16 / 64 page SPI interface STMPE811 16/64 Doc ID 14489 Rev 2 5.2 SPI timing modes The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the "SDAT" and "A0" pins during power-up reset. The following four modes are defined according to this setting. The clocking diagrams of these modes are shown in ON reset. The device always operates in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on the next transaction defined by the CS_n pin being deasserted and asserted. 5.2.1 SPI timing definition Table 9. SPI timing modes CPOL_N (SDAT pin) CPOL CPHA (ADDR pin) Mode 100 0 101 1 010 2 011 3 Table 10. SPI timing specification Symbol Description Timing Unit Min Typ Max tCSS CS_n falling to first capture clock 1 −− µs tCL Clock low period 500 −− ns tCH Clock high period 500 −− ns tLDI Launch clock to MOSI data valid −− 20 ns tLDO Launch clock to MISO data valid −− 330 µs tDI Data on MOSI valid 1 −− µs tCCS Last clock edge to CS_n high 1 −− µs tCSH CS_n high period 2 −− µs |
Similar Part No. - STMPE811_09 |
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Similar Description - STMPE811_09 |
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