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L6563STR Datasheet(PDF) 26 Page - STMicroelectronics

Part No. L6563STR
Description  Enhanced transition-mode PFC controller
Download  42 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6563STR Datasheet(HTML) 26 Page - STMicroelectronics

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Application information
L6563S
26/42
Doc ID 16116 Rev 3
where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this
ripple, related to the amplitude of its 2fL component, will be:
Figure 37
shows a diagram that helps choose the time constant RFF·CFF based on the
amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the
pin, the IC will not work properly if the pin is either left floating or connected directly to
ground.
Figure 37.
RFF·CFF as a function of 3rd harmonic distortion introduced in the input
current
The dynamics of the voltage feedforward input, that is the output of the multiplier, is limited
downwards at 0.8 V (see Figure 36), so that cannot increase any more if the voltage on the
VFF pin is below 0.8 V. This helps to prevent excessive power flow when the line voltage is
lower than the minimum specified value.
6.4
THD optimizer circuit
The L6563S is provided with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (total harmonic distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the high-
frequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This will result in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.
Figure 38
shows the internal block diagram of the THD optimizer circuit.
FF
FF
L
3
C
R
f
2
100
%
D
π
=
 
D %
3
0.1110
0.01
0.1
1
10
f = 50 Hz
L
f = 60 Hz
L
R · C
[s]
FF
FF


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