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MFRC522 Datasheet(PDF) 15 Page - NXP Semiconductors |
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MFRC522 Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 96 page  MFRC522_34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet PUBLIC Rev. 3.4 — 5 March 2010 112134 15 of 96 NXP Semiconductors MFRC522 Contactless reader IC 8.1.4 I2C-bus interface An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I2C-bus interface is implemented according to NXP Semiconductors’ I2C-bus interface specification, rev. 2.1, January 2000. The interface can only act in Slave mode. Therefore the MFRC522 does not implement clock generation or access arbitration. The MFRC522 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode. SDA is a bidirectional line connected to a positive supply voltage using a current source or a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The MFRC522 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode. If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA as defined in the I2C-bus interface specification. See Table 155 on page 76 for timing requirements. Table 14. Address byte 0 register; address MOSI 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 = read 0 = write reserved address Fig 11. I2C-bus interface 001aak590 MFRC522 SDA SCL I2C EA ADR_[5:0] PULL-UP NETWORK CONFIGURATION WIRING PULL-UP NETWORK MICROCONTROLLER |
Similar Part No. - MFRC522_10 |
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Similar Description - MFRC522_10 |
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