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MFRC522 Datasheet(PDF) 8 Page - NXP Semiconductors |
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MFRC522 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 96 page  MFRC522_34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet PUBLIC Rev. 3.4 — 5 March 2010 112134 8 of 96 NXP Semiconductors MFRC522 Contactless reader IC The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using the MfRxReg register’s ParityDisable bit. 8.1 Digital interfaces 8.1.1 Automatic microcontroller interface detection The MFRC522 supports direct interfacing of hosts using SPI, I2C-bus or serial UART interfaces. The MFRC522 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The MFRC522 identifies the host interface by sensing the logic levels on the control pins after the reset phase. This is done using a combination of fixed pin connections. Table 5 shows the different connection configurations. Fig 6. Data coding and framing according to ISO/IEC 14443 A 001aak585 ISO/IEC 14443 A framing at 106 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start odd parity start bit is 1 ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start even parity start bit is 0 burst of 32 subcarrier clocks even parity at the end of the frame Table 5. Connection protocol for detecting different interface types Pin Interface type UART (input) SPI (output) I2C-bus (I/O) SDA RX NSS SDA I2C 001 EA 01EA D7 TX MISO SCL D6 MX MOSI ADR_0 D5 DTRQ SCK ADR_1 D4 - - ADR_2 D3 - - ADR_3 D2 - - ADR_4 D1 - - ADR_5 |
Similar Part No. - MFRC522_10 |
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Similar Description - MFRC522_10 |
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