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LPC2929 Datasheet(PDF) 11 Page - NXP Semiconductors |
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LPC2929 Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 95 page LPC2927_29_4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 14 April 2010 11 of 95 NXP Semiconductors LPC2927/2929 ARM9 microcontroller with CAN, LIN, and USB [1] Bidirectional pad; analog port; plain input; 3-state output; slew rate control; 5 V tolerant; TTL with hysteresis; programmable pull-up/pull-down/repeater. [2] USB pad. [3] Analog pad; analog I/O. [4] Analog I/O pad. 6. Functional description 6.1 Architectural overview The LPC2927/2929 consists of: • An ARM968E-S processor with real-time emulation support • An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllers • Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller and the Power, Clock and Reset Control cluster (also called subsystem). • Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA advanced peripheral bus) for connection to on-chip peripherals clustered in subsystems. • One ARM Peripheral Bus for event router and system control. P0[19]/IN2[3]/ PMAT2[1]/A15 133[4] GPIO0, pin 19 ADC2 IN3 PWM2 MAT1 EXTBUS A15 P3[4]/MAT3[2]/ PMAT2[4]/TXDC1 134[1] GPIO3, pin 4 TIMER3 MAT2 PWM2 MAT4 CAN1 TXD P3[5]/MAT3[3]/ PMAT2[5]/RXDC1 135[1] GPIO3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RXD P2[18]/SCS2[1]/ PCAP1[1]/D16 136[1] GPIO2, pin 18 SPI2 SCS1 PWM1 CAP1 EXTBUS D16 P2[19]/SCS2[0]/ PCAP1[2]/D17 137[1] GPIO2, pin 19 SPI2 SCS0 PWM1 CAP2 EXTBUS D17 P0[20]/IN2[4]/ PMAT2[2]/A16 138[4] GPIO0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16 P0[21]/IN2[5]/ PMAT2[3]/A17 139[4] GPIO0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17 P0[22]/IN2[6]/ PMAT2[4]/A18 140[4] GPIO0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18 VSS(IO) 141 ground for I/O P0[23]/IN2[7]/ PMAT2[5]/A19 142[4] GPIO0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19 P2[20]/ PCAP2[0]/D18 143[1] GPIO2, pin 20 SPI2 SDO PWM2 CAP0 EXTBUS D18 TDI 144[1] IEEE 1149.1 data in, pulled up internally Table 3. LQFP144 pin assignment …continued Pin name Pin Description Function 0 (default) Function 1 Function 2 Function 3 |
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