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LPC2102 Datasheet(PDF) 8 Page - NXP Semiconductors |
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LPC2102 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 37 page LPC2101_02_03_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 2 June 2009 8 of 37 NXP Semiconductors LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers P0.22/AD0.0 32[3] I/O P0.22 — General purpose input/output digital pin. I AD0.0 — ADC 0, input 0. P0.23/AD0.1 33[3] I/O P0.23 — General purpose input/output digital pin. I AD0.1 — ADC 0, input 1. P0.24/AD0.2 34[3] I/O P0.24 — General purpose input/output digital pin. I AD0.2 — ADC 0, input 2. P0.25/AD0.6 38[3] I/O P0.25 — General purpose input/output digital pin. I AD0.6 — ADC 0, input 6. P0.26/AD0.7 39[3] I/O P0.26 — General purpose input/output digital pin. I AD0.7 — ADC 0, input 7. P0.27/TRST/ CAP2.0 8[1] I/O P0.27 — General purpose input/output digital pin. I TRST — Test Reset for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). I CAP2.0 — Capture input for Timer 2, channel 0. P0.28/TMS/ CAP2.1 9[1] I/O P0.28 — General purpose input/output digital pin. I TMS — Test Mode Select for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). I CAP2.1 — Capture input for Timer 2, channel 1. P0.29/TCK/ CAP2.2 10[1] I/O P0.29 — General purpose input/output digital pin. I TCK — Test Clock for JTAG interface. This clock must be slower than 1 ⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). I CAP2.2 — Capture input for Timer 2, channel 2. P0.30/TDI/ MAT3.3 15[1] I/O P0.30 — General purpose input/output digital pin. I TDI — Test Data In for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). O MAT3.3 — PWM output 3 for Timer 3. P0.31/TDO 16[1] O P0.31 — General purpose output only digital pin. O TDO — Test Data Out for JTAG interface. If DBGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode). RTCX1 20[7][8] I Input to the RTC oscillator circuit. Input voltage must not exceed 1.8 V. RTCX2 25[7][8] O Output from the RTC oscillator circuit. RTCK 26[7] I/O Returned test clock output: Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. XTAL1 11 I Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTAL2 12 O Output from the oscillator amplifier. DBGSEL 27 I Debug select: When LOW, the part operates normally. When externally pulled HIGH at reset, P0.27 to P0.31 are configured as JTAG port, and the part is in Debug mode[9]. Input with internal pull-down. RST 6 I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. Table 3. Pin description …continued Symbol Pin Type Description |
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Similar Description - LPC2102 |
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