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LPC1311FHN33 Datasheet(PDF) 37 Page - NXP Semiconductors |
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LPC1311FHN33 Datasheet(HTML) 37 Page - NXP Semiconductors |
37 / 60 page LPC1311_13_42_43_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 6 May 2010 37 of 60 NXP Semiconductors LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] All other blocks disabled in the PDSLEEPCFG register. 9.3 Electrical pin characteristics Table 10. Power consumption in Deep-sleep mode for individual analog blocks Tamb = 25 °C; VDD = 3.3 V. Analog block enabled in PDSLEEPCFG register Conditions Typical IDD[1] USB PLL [2] 39 μA System PLL [2] 39 μA System oscillator [2] 197 μA BOD [2] 74 μA IRC [2] 36 μA IRC output [2] 27 μA Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 14. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. IOH (mA) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 VOH (V) 2 T = 85 °C 25 °C −40 °C |
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