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LH79525N0Q100A1 Datasheet(PDF) 7 Page - NXP Semiconductors |
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LH79525N0Q100A1 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 64 page  System-on-Chip LH79524/LH79525 Preliminary data sheet Rev. 01 — 16 July 2007 7 NXP Semiconductors M3 PB7/INT1/UARTTX0/ UARTIRTX0 I/O General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmit- ted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1. N7 PC0/A16 I/O General Purpose I/O Signal — Port C0; multiplexed with Address A16 R6 PC1/A17 I/O General Purpose I/O Signal — Port C1; multiplexed with Address A17 T5 PC2/A18 I/O General Purpose I/O Signal — Port C2; multiplexed with Address A18 P6 PC3/A19 I/O General Purpose I/O Signal — Port C3; multiplexed with Address A19 R5 PC4/A20 I/O General Purpose I/O Signal — Port C4; multiplexed with Address A20 T4 PC5/A21 I/O General Purpose I/O Signal — Port C5; multiplexed with Address A21 P5 PC6/A22/nFWE I/O General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND Flash Write Enable R4 PC7/A23/nFRE I/O General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND Flash Read Enable P15 PD0/D8 I/O General Purpose I/O Signal — Port D0; multiplexed with Data D8 P14 PD1/D9 I/O General Purpose I/O Signal — Port D1; multiplexed with Data D9 N13 PD2/D10 I/O General Purpose I/O Signal — Port D2; multiplexed with Data D10 T15 PD3/D11 I/O General Purpose I/O Signal — Port D3; multiplexed with Data D11 N12 PD4/D12 I/O General Purpose I/O Signal — Port D4; multiplexed with Data D12 T14 PD5/D13 I/O General Purpose I/O Signal — Port D5; multiplexed with Data D13 P12 PD6/D14 I/O General Purpose I/O Signal — Port D6; multiplexed with Data D14 T13 PD7/D15 I/O General Purpose I/O Signal — Port D7; multiplexed with Data D15 B12 PE0/LCDLP/ LCDHRLP I/O General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and AD-TFT/HR-TFT Line Pulse D11 PE1/LCDDCLK I/O General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock B13 PE2/LCDPS I/O General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save C13 PE3/LCDCLS I/O General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock D12 PE4/LCDDSPLEN/ LCDREV I/O General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power Enable and LCD Reverse B16 PE5/LCDVDDEN I/O General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable B15 PE6/LCDVEEN/ LCDMOD I/O General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power Enable and MOD D14 PE7/nWAIT/nDEOT I/O General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA End of Transfer A8 PF0/LCDVD6 I/O General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6 A9 PF1/LCDVD7 I/O General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7 B9 PF2/LCDVD8 I/O General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8 C9 PF3/LCDVD9 I/O General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9 B10 PF4/LCDVD10 I/O General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10 A11 PF5/LCDVD11 I/O General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11 B11 PF6/LCDEN/LCDSPL I/O General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left A12 PF7/LCDFP/LCDSPS I/O General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver Counter reset A5 PG0/ETHERTXEN I/O General Purpose I/O Signals — Port G0; multiplexed with Ethernet TX Enable B6 PG1/ETHERTXCLK I/O General Purpose I/O Signals — Port G1; multiplexed with Ethernet TX Clock A6 PG2/LCDVD0 I/O General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0 C7 PG3/LCDVD1 I/O General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1 B7 PG4/LCDVD2 I/O General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2 Table 2. LH79524 Pin Descriptions (Cont’d) LFBGA PIN SIGNAL NAME TYPE DESCRIPTION |
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