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LH7A400N0G000B5 Datasheet(PDF) 10 Page - NXP Semiconductors |
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LH7A400N0G000B5 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 65 page  LH7A400 32-Bit System-on-Chip 10 Rev. 01 — 16 July 2007 Preliminary data sheet NXP Semiconductors L6 P4 PG2/ nPCIOR • GPIO Port G • I/O Read Strobe for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG2 No Change 8 mA I/O M6 R3 PG3/ nPCIOW • GPIO Port G • I/O Write Strobe for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG3 No Change 8 mA I/O N6 T2 PG4/nPCREG • GPIO Port G • Register Memory Access for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG4 No Change 8 mA I/O M7 P5 PG5/nPCCE1 • GPIO Port G • Card Enable 1 for PC Card (PCMCIA or CF) in single or dual card mode. This signal and nPCCE2 are used by the PC Card for decoding low and high byte accesses. LOW: PG5 No Change 8 mA I/O M8 R4 PG6/nPCCE2 • GPIO Port G • Card Enable 2 for PC Card (PCMCIA or CF) in single or dual card mode. This signal and nPCCE1 are used by the PC Card for decoding low and high byte accesses. LOW: PG6 No Change 8 mA I/O N4 T3 PG7/PCDIR • GPIO Port G • Direction for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG7 No Change 8 mA I/O P4 P6 PH0/ PCRESET1 • GPIO Port H • Reset Card 1 for PC Card (PCMCIA or CF) in sin- gle or dual card mode Input: PH0 No Change 8 mA I/O R4 T4 PH1/CFA8/ PCRESET2 • GPIO Port H • Address Bit 8 for PC Card (CF) in single card mode • Reset Card 2 for PC Card (PCMCIA or CF) in dual card mode Input: PH1 No Change 8 mA I/O T4 M7 PH2/ nPCSLOTE1 • GPIO Port H • Enable Card 1 for PC Card (PCMCIA or CF) in sin- gle or dual card mode. This signal is used for gating other control signals to the appropriate PC Card. Input: PH2 No Change 8 mA I/O N7 T5 PH3/CFA9/ PCMCIAA25/ nPCSLOTE2 • GPIO Port H • Address Bit 9 for PC Card (CF) in single card mode • Address Bit 25 for PC Card (PCMCIA) in single card mode • Enable Card 2 for PC Card (PCMCIA or CF) in dual card mode. This signal is used for gating other control signals to the appropriate PC Card. Input: PH3 No Change 8 mA I/O P8 R6 PH4/ nPCWAIT1 • GPIO Port H • WAIT Signal for Card 1 for PC Card (PCMCIA or CF) in single or dual card mode Input: PH4 No Change 8 mA I/O P5 R7 PH5/CFA10/ PCMCIAA24/ nPCWAIT2 • GPIO Port H • Address Bit 10 for PC Card (CF) in single card mode • Address Bit 24 for PC Card (PCMCIA) in single card mode • WAIT Signal for Card 2 for PC Card (PCMCIA or F) in dual card mode Input: PH5 No Change 8 mA I/O R5 P7 PH6/ nAC97RESET • GPIO Port H • Audio Codec (AC97) Reset Input: PH6 No Change 8 mA I/O T5 T6 PH7/ nPCSTATRE • GPIO Port H • Status Read Enable for PC Card (PCMCIA or F) in single or dual card mode Input: PH7 No Change 8 mA I/O R6 T7 LCDFP LCD Frame Synchronization pulse LOW LOW 12 mA O R8 R9 LCDLP LCD Line Synchronization pulse LOW LOW 12 mA O Table 3. Functional Pin List (Cont’d) BGA PIN LFBGA PIN SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE I/O NOTES |
Similar Part No. - LH7A400N0G000B5 |
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Similar Description - LH7A400N0G000B5 |
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