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LH7A400N0G000B5 Datasheet(PDF) 9 Page - NXP Semiconductors |
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LH7A400N0G000B5 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 65 page  32-Bit System-on-Chip LH7A400 Preliminary data sheet Rev. 01 — 16 July 2007 9 NXP Semiconductors T1 N4 PC5/ LCDCLS • GPIO Port C • HR-TFT Row Driver Clock LOW: PC5 No Change 12 mA I/O T2 R2 PC6/LCDHR- LP • GPIO Port C • LCD Latch Pulse LOW: PC6 No Change 12 mA I/O R2 N5 PC7/ LCDSPL • GPIO Port C • LCD Start Pulse Left LOW: PC7 No Change 12 mA I/O M11 M9 PD0/LCDVD8 • GPIO Port D • LCD Video Data Bus LOW: PD0 LOW if PINMUX: PDOCON = 1 (bit 1); otherwise, No Change 12 mA I/O L11 K10 PD1/LCDVD9 LOW: PD1 I/O K8 P10 PD2/LCDVD10 LOW: PD2 I/O N11 T11 PD3/LCDVD11 LOW: PD3 I/O R9 T12 PD4/LCDVD12 LOW: PD4 I/O T9 R11 PD5/LCDVD13 LOW: PD5 I/O P10 R12 PD6/LCDVD14 LOW: PD6 I/O R10 T13 PD7/LCDVD15 LOW: PD7 I/O L10 T9 PE0/LCDVD4 • GPIO Port E • LCD Video Data Bus Input: PE0 LOW if PINMUX: PDOCON or PEOCON = 1 (bits [1:0]); otherwise No Change 12 mA I/O N10 K9 PE1/LCDVD5 Input: PE1 I/O M9 T10 PE2/LCDVD6 Input: PE2 I/O M10 R10 PE3/LCDVD7 Input: PE3 I/O A6 A5 PF0/INT0 • GPIO Port F • External FIQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. Input: PF0 No Change 8 mA I/O 3 B6 B4 PF1/INT1 • GPIO Port F • External IRQ Interrupts. Interrupts can be level or edge triggered and are internally debounced. Input: PF1 No Change 8 mA I/O 3 C6 E7 PF2/INT2 Input: PF2 No Change 8 mA I/O 3 H8 B3 PF3/INT3 • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. Input: PF3 No Change 8 mA I/O 3 B5 C5 PF4/INT4/ SCVCCEN • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Smart Card Supply Voltage Enable Input: PF4 LOW if SCI is Enabled; otherwise No Change 8 mA I/O 3 D6 D6 PF5/INT5/ SCDETECT • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Smart Card Detection Input: PF5 No Change 8 mA I/O 3 E6 A4 PF6/INT6/ PCRDY1 • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Ready for Card 1 for PC Card (PCMCIA or CF) in single or dual card mode Input: PF6 No Change 8 mA I/O 3 C5 A3 PF7/INT7/ PCRDY2 • GPIO Port F • External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. • Ready for Card 2 for PC Card (PCMCIA or CF) in single or dual card mode Input: PF7 No Change 8 mA I/O 3 R3 M6 PG0/nPCOE • GPIO Port G • Output Enable for PC Card (PCMCIA or CF) in single or dual card mode LOW: PG0 No Change 8 mA I/O T3 T1 PG1/nPCWE • GPIO Port G • Write Enable for PC Card (PCMCIA or CF) in sin- gle or dual card mode LOW: PG1 No Change 8 mA I/O Table 3. Functional Pin List (Cont’d) BGA PIN LFBGA PIN SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE I/O NOTES |
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