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ADS1113IRUGT Datasheet(PDF) 16 Page - Texas Instruments |
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ADS1113IRUGT Datasheet(HTML) 16 Page - Texas Instruments |
16 / 36 page ADS1113 ADS1114 ADS1115 SBAS444B – MAY 2009 – REVISED OCTOBER 2009 www.ti.com SMBus ALERT RESPONSE An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are When configured in latching mode (COMP_LAT = '1' transmitted across the I2C bus in groups of eight bits. in the Config register), the ALERT/RDY pin can be To send a bit on the I2C bus, the SDA line is driven to implemented with an SMBus alert. The pin asserts if the appropriate level while SCL is low (a low on SDA the comparator detects a conversion that exceeds an indicates the bit is zero; a high indicates the bit is upper or lower threshold. This interrupt is latched and one). Once the SDA line settles, the SCL line is can be cleared only by reading conversion data, or by brought high, then low. This pulse on SCL clocks the issuing a successful SMBus alert response and SDA bit into the receiver shift register. If the I2C bus reading the asserting device I2C address. If is held idle for more than 25ms, the bus times out. conversion data exceed the upper or lower thresholds after being cleared, the pin reasserts. This assertion The I2C bus is bidirectional: the SDA line is used for does not affect conversions that are already in both transmitting and receiving data. When the progress. The ALERT/RDY pin, as with the SDA pin, master reads from a slave, the slave drives the data is an open-drain pin. This architecture allows several line; when the master sends to a slave, the master devices to share the same interface bus. When drives the data line. The master always drives the disabled, the pin holds a high state so that it does not clock line. The ADS1113/4/5 never drive SCL, interfere with other devices on the same bus line. because they cannot act as a master. On the ADS1113/4/5, SCL is an input only. When the master senses that the ALERT/RDY pin has latched, it issues an SMBus alert command Most of the time the bus is idle; no communication (00011001) to the I2C bus. Any ADS1114/5 data occurs, and both lines are high. When communication converters on the I2C bus with the ALERT/RDY pins is taking place, the bus is active. Only master devices asserted respond to the command with the slave can start a communication and initiate a START address. In the event that two or more ADS1114/5 condition on the bus. Normally, the data line is only data converters present on the bus assert the latched allowed to change state while the clock line is low. If ALERT/RDY pin, arbitration during the address the data line changes state while the clock line is response portion of the SMBus alert decides which high, it is either a START condition or a STOP device clears its assertion. The device with the lowest condition. A START condition occurs when the clock I2C address always wins arbitration. If a device loses line is high and the data line goes from high to low. A arbitration, it does not clear the comparator output pin STOP condition occurs when the clock line is high assertion. The master then repeats the SMBus alert and the data line goes from low to high. response until all devices have had the respective After the master issues a START condition, it sends a assertions cleared. In window comparator mode, the byte that indicates which slave device it wants to SMBus alert status bit indicates a '1' if signals exceed communicate with. This byte is called the address the high threshold and a '0' if signals exceed the low byte. Each device on an I2C bus has a unique 7-bit threshold. address to which it responds. The master sends an address in the address byte, together with a bit that I 2C INTERFACE indicates whether it wishes to read from or write to the slave device. The ADS1113/4/5 communicate through an I2C interface. I2C is a two-wire open-drain interface that Every byte transmitted on the I2C bus, whether it is supports multiple devices and masters on a single address or data, is acknowledged with an bus. Devices on the I2C bus only drive the bus lines acknowledge bit. When the master has finished low by connecting them to ground; they never drive sending a byte (eight data bits) to a slave, it stops the bus lines high. Instead, the bus wires are pulled driving SDA and waits for the slave to acknowledge high by pull-up resistors, so the bus wires are high the byte. The slave acknowledges the byte by pulling when no device is driving them low. This way, two SDA low. The master then sends a clock pulse to devices cannot conflict; if two devices drive the bus clock the acknowledge bit. Similarly, when the master simultaneously, there is no driver contention. has finished reading a byte, it pulls SDA low to acknowledge this to the slave. It then sends a clock Communication on the I2C bus always takes place pulse to clock the bit. (The master always drives the between two devices, one acting as the master and clock line.) the other as the slave. Both masters and slaves can read and write, but slaves can only do so under the A not-acknowledge is performed by simply leaving direction of the master. Some I2C devices can act as SDA high during an acknowledge cycle. If a device is masters or slaves, but the ADS1113/4/5 can only act not present on the bus, and the master attempts to as slave devices. address it, it receives a not-acknowledge because no device is present at that address to pull the line low. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS1113 ADS1114 ADS1115 |
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