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CS1500-FSZ Datasheet(PDF) 7 Page - Cirrus Logic |
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CS1500-FSZ Datasheet(HTML) 7 Page - Cirrus Logic |
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7 / 22 page  CS1500 DS849A5 7 May ?$shortyear> CONFIDENTIAL 3. INTRODUCTION Figure 9. CS1500 Block Diagram The CS1500 digital power factor controller operates in variable on-time, variable frequency, discontinuous conduction mode (DCM). The CS1500 uses a proprietary digital algorithm to maximize the efficiency and reduce the conductive EMI. The analog-to-digital converter (ADC) shown in the CS1500 block diagram in Figure 9 is used to sense the PFC output voltage ( Vlink ) and the rectified AC line voltage ( Vrect ) by measuring currents through their respective resistors. The magnitudes of these currents are measured as a proportion of a reference current (IREF) that functions as the reference for the ADCs. The digital signal is then processed in a control algorithm which determines the behavior of the CS1500 during start-up, normal operation, and under fault conditions, such as brownout, overvoltage, overcurrent, overpower, and over-temperature conditions. • DCM with Variable On-Time, Variable Switching Fre- quency The CS1500 PFC switching frequency varies with the Vrect on a cycle-by-cycle basis, and its digital algorithm calculates the on-time accordingly for unity power factor. Unlike traditional Critical Conduction Mode (CRM) PFC controller, CS1500 operates at its low switching frequen- cy near the zero-crossing point of the AC input voltage, even no switching at all, and it operates at its high switch- ing frequency at the peak of its AC input voltage (this is the opposite of the switching frequency profile for a CRM PFC controller), thus CS1500 reduces switching losses especially under light-load conditions, spreads conducted EMI energy peaks over a wide frequency band and in- creases overall system efficiency. • Optimized Digital Loop Compensation The proprietary digital control engine optimizes the feed- back error signal using an adaptive control algorithm, im- proves system stability and transient response. No external feedback error signal compensation components are required. • Overcurrent Mitigation The CS1500s digital controller algorithm limits the ON time of the Power MOSFET by the following equation: Where Ton is the max time that the power MOSFET is turned on and Vrect is the rectified line voltage. In the event of a sudden line surge or sporadic, high dv/dt line voltages, this equation may not limit the ON time appro- priately. For this type of line disturbance, additional pro- tection mechanisms such as fusible resistors, fast-blow fuses, or other current-limiting devices are recommend- ed. • Over Voltage Protection Under steady-state conditions, the voltage loop keeps PFC output voltage close to its nominal value. Under light load startup or feedback loop open conditions, the output voltage may pass the overvoltage protection threshold. The digital control engine initiates a fast response loop to shut down gate driving signal to reduce the energy deliv- ered to the output for PFC capacitor protection. When the link voltage drop below VOVP-VOVP(Hy), PFC resumes normal operation. IAC FB STBY 3 4 2 CS1500 GD 6 VDD 7 NC 8 GND 5 Processor Logic NC 1 PWM Driver Oscillator Protection ADC T on 0.001126 V rect ------------------------- ≤ |
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