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PSMN3R0-30YL Datasheet(PDF) 6 Page - NXP Semiconductors |
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PSMN3R0-30YL Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 14 page PSMN3R0-30YL_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 28 December 2009 6 of 14 NXP Semiconductors PSMN3R0-30YL N-channel TrenchMOS logic level FET [1] Tested to JEDEC standards where applicable. Source-drain diode VSD source-drain voltage IS =25A; VGS =0V; Tj = 25 °C; see Figure 17 - 0.82 1.2 V trr reverse recovery time IS =20A; dIS/dt = -100 A/µs; VGS =0V; VDS =20V -35 - ns Qr recovered charge - 29 - nC Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Fig 5. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 6. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 7. Drain-source on-state resistance as a function of drain current; typical values Fig 8. Forward transconductance as a function of drain current; typical values 003aac566 0 20 40 60 80 0.0 1.0 2.0 3.0 VGS (V) ID (A) Tj = 150 °C 25 °C 003aac567 0 20 40 60 80 100 120 140 160 024 6 8 10 VDS (V) ID (A) VGS (V) = 3.2 2.2 2.4 2.6 2.8 3 4.5 10 003aac570 2 4 6 8 0 20 40 60 80 100 ID (A) RDSon (m Ω) VGS (V) = 3.2 4.5 10 003aac571 40 60 80 100 120 140 020 40 60 ID (A) gfs (S) |
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