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KT11P2JM Datasheet(PDF) 2 Page - Texas Instruments

Part No. KT11P2JM
Description  High-Integration, High-Efficiency Power Solution Using DC/DC Converters With DVFS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

KT11P2JM Datasheet(HTML) 2 Page - Texas Instruments

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Power Requirements
www.ti.com
Another potential problem with improper supply sequencing is bus contention. Bus contention is a
condition when the processor and another device both attempt to control a bi-directional bus during power
up. Bus contention may also affect I/O reliability. Power supply designers should check the requirements
regarding bus contention for individual devices.
The power-on sequencing for the OMAP-L138, TMS320C6742, TMS320C6746, and TMS320C6748 are
shown in the Power Requirements table below. There is no specific required voltage ramp rate for any of
the supplies as long as the 3.3V rail never exceeds the 1.8V rail by more than 2V.
Also, in order to reduce the power consumption of the processor core, the Dynamic Voltage and
Frequency Scaling (DVFS) is used in the reference design. DVFS is a power management technique used
while the system-on-chip (SoC) is actively processing. This technique matches the operating frequency of
the hardware to the performance requirement of the active application scenario. Whenever clock
frequencies are lowered, operating voltages are also lowered as well to achieve power savings. In the
reference design, the TPS65023 is used that can scale its output voltage. It supports all five DVFS voltage
values (0.95V, 1V, 1.2V, 1.27V, and 1.35V) defined for VDD_MPU.
2
Power Requirements
The power requirements are as specify in the table.
VOLTAGE
(1) (2)
Imax
SEQUENCING
TIMING
PIN NAME
TOLERANCE
(V)
(mA)
ORDER
DELAY
I/O
RTC_CVDD
1.2
1
–25%, +10%
1
(3)
Core
CVDD
(4)
1.0 / 1.1 / 1.2
600
–9.75%, +10%
2
I/O
RVDD, PLL0_VDDA,
1.2
200
–5%, +10%
3
PLL1_VDDA, SATA_VDD,
USB_CVDD, USB0_VDDA12
I/O
USB0_VDDA18, USB1_VDDA18,
1.8
180
±5%
4
DDR_DVDD18, SATA_VDDR,
DVDD18
I/O
USB0_VDDA33, USB1_VDDA33
3.3
24
±5%
5
I/O
DVDD3318_A, DVDD3318_B,
1.8 / 3.3
50 / 90
(5)
±5%
4 / 5
DVDD3318_C
(1)
If 1.8-V LVCMOS is used, power rails up with the 1.8-V rails. If 3.3-V LVCMOS is used, power it up with the ANALOG33 rails
(VDDA33_USB0/1)
(2)
There is no specific required voltage ramp rate for any of the supplies LVCMOS33 (USB0_VDDA33, USB1_VDDA33) never
exceeds STATIC18 (USB0_VDDA18, USB1_VDDA18, DDR_DVDD18, SATA_VDDR, DVDD18) by more than 2 V.
(3)
If RTC is not used/maintained on a separate supply, it can be included in the STATIC12 (fixed 1.2 V) group.
(4)
If using CVDD at fixed 1.2 V, all 1.2-V rails may be combined.
(5)
If DVDD3318_A, B, and C are powered independently, maximum power for each rail will be 1/3 the above maximum power.
2
High-Integration, High-Efficiency Power Solution Using DC/DC Converters With
SLVA340A – June 2009 – Revised May 2010
DVFS
Copyright © 2009–2010, Texas Instruments Incorporated


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