1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

28

27

26

25

24

23

22

21

20

ABDECAY

AOUT1

VM

VM

AOUT2

AISEN

ABSTEP

ABUSM0

ABDIR

ABVREF

BISEN

CDVREF

CDDECAY

ABENBLn

V3P3

BOUT2

BOUT1

CDSTEP

CDUSM0

CDDIR

CDENBLn

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PGND

PGND

PGND

PGND

PGND

PGND

Solder these

pins to copper

heatsink area

PGND

PGND

PGND

PGND

PGND

VCP

CP2

CP1

VM

DOUT2

DISEN

DOUT1

VM

ABUSM1

ABRESETn

CISEN

COUT2

CDRESETn

COUT1

CDUSM1

PGND

Solder these

pins to copper

heatsink area

DRV8821

SLVS912C – JANUARY 2009 – REVISED JANUARY 2010

www.ti.com

DCA PACKAGE

ABSOLUTE MAXIMUM RATINGS

(1) (2)

over operating free-air temperature range (unless otherwise noted)

Power supply voltage range

–0.3 to 34

V

–0.5 to 5.75

V

Peak motor drive output current, t < 1 ms

Internally limited

1.5

A

Continuous total power dissipation

See Dissipation Ratings Table

Operating virtual junction temperature range

–40 to 150

°C

Operating ambient temperature range

–40 to 85

°C

Storage temperature range

–60 to 150

°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

(3)

(4)

Power dissipation and thermal limits must be observed.

DISSIPATION RATINGS

DERATING FACTOR

BOARD

PACKAGE

75.7°C/W

13.2 mW/°C

1.65 W

1.06 W

0.86 W

32°C/W

31.3 mW/°C

3.91 W

2.50 W

2.03 W

DCA

30.3°C/W

33 mW/°C

4.13 W

2.48 W

2.15 W

22.3°C/W

44.8 mW/°C

5.61 W

3.59 W

2.91 W

(1)

The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper.

(2)

side.

(3)

The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and

solid 1-oz internal ground plane.

(4)

side and solid 1-oz internal ground plane.

4

Submit Documentation Feedback

Copyright © 2009–2010, Texas Instruments Incorporated

Product Folder Link(s): DRV8821