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CC8520RHAT Datasheet(PDF) 6 Page - Texas Instruments |
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CC8520RHAT Datasheet(HTML) 6 Page - Texas Instruments |
6 / 17 page CC8520 WWW.TI.COM SWRS091A – MARCH 2010 6 Copyright © 2010, Texas Instruments Incorporated PIN PIN NAME PIN TYPE DESCRIPTION 10 IODVDD Power (I/O pads) Digital power supply for the digital I/Os in the SPI interface and GIO1-GIO3. 11 RSTN Digital Input (pull-up) Active-low device reset 12 IOVDD Power (I/O pins) Digital power supply for the RSTN and MCLK digital I/O pins. 13 MCLK GIO4 Digital I/O 1 Master clock output for external audio devices General-purpose digital I/O pin 4 14 BCLK GIO5 Digital I/O 1 I2S/DSP audio interface bit clock (in/out) General-purpose digital I/O pin 5 15 WCLK GIO6 Digital I/O 1 I2S/DSP audio interface word clock (in/out) General-purpose digital I/O pin 6 16 AD0 GIO7 Digital I/O 1 I2S/DSP audio interface data line 0 (in/out) General-purpose digital I/O pin 7 17 AD1 GIO8 Digital I/O 1 I2S/DSP audio interface data line 1 (in/out) General-purpose digital I/O pin 8 18 IOVDD Power (I/O pins) Digital power supply for the digital I/Os in audio interface (BCLK-AD2). 19 AD2 GIO9 Digital I/O 2 I2S/DSP audio interface data line 2 (in/out) Configurable with PurePath™ Wireless Configurator 20 AVDD Power (Analog) 2.0-3.6V analog power supply connection 21 XI Analog I/O Crystal oscillator pin input, or external clock input (48 MHz) 22 XO Analog I/O Crystal oscillator pin output (48 MHz) 23 AVDD Power (Analog) Analog power supply connection 24 RF_P RF I/O Positive differential RF input signal to LNA in receive mode Positive differential RF output signal from PA in transmit mode 25 RF_N RF I/O Negative differential RF input signal to LNA in receive mode Negative differential RF output signal from PA in transmit mode 26 AVDD Power (Analog) Analog power supply connection 27 AVDD Power (Analog) Analog power supply connection 28 AVDD Power (Analog) Analog power supply connection 29 VBAT Analog input Battery voltage supervisor (threshold level programmable by external resistor to positive battery terminal) 30 RBIAS Analog output External precision bias resistor for reference current. 56 k Ω, ±1% 31 AVDD Power (Analog) Analog power supply connection (Guard ring AVDD connection for digital noise isolation) 32 SCL GIO10 Digital I/O 1 I2C master clock line. Must be connected to external pull-up General-purpose digital I/O pin 10 33 SDA GIO11 Digital I/O 1 I2C master data line. Must be connected to external pull-up General-purpose digital I/O pin 11 34 GIO12 Digital I/O 1 General-purpose digital I/O pin 12 35 GIO13 Digital I/O 1 General-purpose digital I/O pin 13 36 XLNAEN Digital I/O 2 Control external LNA 37 IODVDD Power (I/O pads) Digital power supply for SCL-GIO15 pins. 38 XPAEN Digital I/O 2 Control external PA |
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