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CS4953XX Datasheet(PDF) 17 Page - Cirrus Logic |
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CS4953XX Datasheet(HTML) 17 Page - Cirrus Logic |
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17 / 36 page  CS4953xx Data Sheet 32-bit Audio Decoder DSP Family DS705PP6 Copyright 2009 Cirrus Logic 17 5.13 Switching Characteristics — Serial Control Port - I2C Master Mode Figure 6. Serial Control Port - I2C Master Mode Timing Parameter Symbol Min Max Units SCP_CLK frequency1 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. fiicck -400 kHz SCP_CLK low time tiicckl 1.25 - µs SCP_CLK high time tiicckh 1.25 - µs SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition tiicckcmd 1.25 µs START condition to SCP_CLK falling tiicstscl 1.25 - µs SCP_CLK falling to STOP condition tiicstp 2.5 - µs Bus free time between STOP and START conditions tiicbft 3- µs Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 ns Hold time SCP_SDA input after SCP_CLK falling tiich 20 - ns SCP_CLK low to SCP_SDA out valid tiicdov -36 ns SCP_CLK SCP_SDA 0 1 6780 1 7 tiicckl tiicckh tiicsu tiich A6 A0 R/W ACK LSB 8 ACK MSB tiicstp 6 tiicdov tiicbft tiicstscl tiicckcmd fiicck tiicckcmd tiicf tiicr |
Similar Part No. - CS4953XX_09 |
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Similar Description - CS4953XX_09 |
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