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CS4205 Datasheet(PDF) 4 Page - Cirrus Logic |
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CS4205 Datasheet(HTML) 4 Page - Cirrus Logic |
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4 / 81 page  CS4205 4 DS489PP4 10.1.3 New Warm Reset .............................................................................................. 59 10.1.4 Register Reset .................................................................................................. 59 10.2 Powerdown Controls ...................................................................................................... 60 11. CLOCKING ........................................................................................................................... 62 11.1 PLL Operation (External Clock) ..................................................................................... 62 11.2 24.576 MHz Crystal Operation ....................................................................................... 62 11.3 Secondary Codec Operation .......................................................................................... 62 12. ANALOG HARDWARE DESCRIPTION ............................................................................... 64 12.1 Analog Inputs ................................................................................................................. 64 12.1.1 Line Inputs ......................................................................................................... 64 12.1.2 CD Input ............................................................................................................ 64 12.1.3 Microphone Inputs ............................................................................................. 65 12.1.4 PC Beep Input ................................................................................................... 65 12.1.5 Phone Input ....................................................................................................... 65 12.2 Analog Outputs .............................................................................................................. 65 12.2.1 Stereo Output .................................................................................................... 66 12.2.2 Mono Output ..................................................................................................... 66 12.3 Miscellaneous Analog Signals ....................................................................................... 66 12.4 Power Supplies .............................................................................................................. 66 12.5 Reference Design ..........................................................................................................67 13. GROUNDING AND LAYOUT .............................................................................................. 68 14. PIN DESCRIPTIONS ....................................................................................................... 70 15. PARAMETER AND TERM DEFINITIONS ............................................................................ 77 16. REFERENCE DESIGN ..................................................................................................... 79 17. REFERENCES ...................................................................................................................... 80 18. PACKAGE DIMENSIONS ..................................................................................................... 81 LIST OF FIGURES Figure 1. Power Up Timing............................................................................................................ 10 Figure 2. Codec Ready from Start-up or Fault Condition .............................................................. 10 Figure 3. Clocks ............................................................................................................................ 10 Figure 4. Data Setup and Hold...................................................................................................... 11 Figure 5. PR4 Powerdown and Warm Reset ................................................................................ 11 Figure 6. Test Mode ...................................................................................................................... 11 Figure 7. AC-link Connections....................................................................................................... 12 Figure 8. CS4205 Mixer Diagram..................................................................................................14 Figure 9. Digital Signal Path Overview..........................................................................................15 Figure 10. Analog Centric Mode.................................................................................................... 17 Figure 11. Digital Centric Mode..................................................................................................... 17 Figure 12. Host Processing Mode .................................................................................................17 Figure 13. Multi-Channel Mode ..................................................................................................... 17 Figure 14. AC-link Input and Output Framing................................................................................ 18 Figure 15. Serial Data Port: Six Channel Circuit ........................................................................... 54 Figure 16. Digital Docking Connection Diagram ........................................................................... 55 Figure 17. Serial Data Format 0 (I2S) ...........................................................................................56 Figure 18. Serial Data Format 1 (Left Justified) ............................................................................ 56 Figure 19. Serial Data Format 2 (Right Justified, 20-bit data) ....................................................... 56 Figure 20. Serial Data Format 3 (Right Justified, 16-bit data) ....................................................... 56 Figure 21. ZV Port Format (I2S, 16-bit data)................................................................................. 57 Figure 22. S/PDIF Output.............................................................................................................. 58 Figure 23. PLL External Loop Filter............................................................................................... 62 Figure 24. External Crystal............................................................................................................ 63 |
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