ADC1412D065 datasheet(22/37 Pages) NXP

Part #	ADC1412D065

Description	Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs

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Manufacturer	NXP [NXP Semiconductors]

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ADC1412D065_080_105_125_2

Objective data sheet

Rev. 02 — 4 June 2009

22 of 37

NXP Semiconductors

ADC1412D065/080/105/125

Dual 14-bit ADC 65, 80, 105 or 125 Msps

If single-ended is implemented without setting SE_SEL to the appropriate value, the

unused pin should be connected to ground via a capacitor.

11.4.3 Duty cycle stabilizer

The duty cycle stabilizer can improve the overall performances of the ADC by

compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is

active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of

between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN =

0), the input clock signal should have a duty cycle of between 45 % and 55 %.

11.4.4 Clock input divider

The ADC1412D contains an input clock divider that divides the incoming clock by a factor

of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher

clock frequency with better jitter performance, leading to a better SNR result once

acquisition has been performed.

11.5 Digital outputs

11.5.1 Digital output buffers: CMOS mode

The digital output buffers can be conﬁgured as CMOS by setting bit LVDS/CMOS to 0 (see

Table 22).

Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS

digital output buffer is shown in Figure 23. The buffer is powered by a separate

OGND/VDDO to ensure 1.8 V to 3.4 V compatibility and is isolated from the ADC core.

Each buffer can be loaded by a maximum of 10 pF.

The output resistance is 50

Ω and is the combination of the an internal resistor and the

equivalent output resistance of the buffer. There is no need for an external damping

resistor. The drive strength of both data and DAV buffers can be programmed via the SPI

in order to adjust the rise and fall times of the output digital signals (see Table 29):

Fig 23. CMOS digital output buffer

VDDO

ESD

PACKAGE

PARASITICS

OGND

Dx

005aaa057

50

Ω

LOGIC

DRIVER

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