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ADC1215S Datasheet(PDF) 15 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 15 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
15 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
10.3 SPI timings
[1]
Typical values measured at VDDA(3V) =3V, VDDO = 1.8 V, VDDA(5V) =5V; Tamb =25 °C and CL =5pF;
minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at
VDDA(3V) =3 V, VDDO = 1.8 V, VDDA(5V) =5V, VINP − VINM = −1 dBFS; internal reference mode; applied to
CMOS and LVDS interface; unless otherwise specified
Table 9.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI timings
tw(SCLK)
SCLK pulse width
40
-
-
ns
tw(SCLKH)
SCLK pulse width HIGH
16
-
-
ns
tw(SCLKL)
SCLK pulse width LOW
16
-
-
ns
tsu
set-up time
data to SCLKH
5
-
-
ns
CS to SCLKH
5
-
-
ns
th
hold time
data to SCLKH
2
-
-
ns
CS to SCLKH
2
-
-
ns
fclk(max)
maximum clock frequency
-
-
25
MHz
Fig 6.
SPI timing
tsu
SDIO
SCLK
R/W
W1
W0
A12
A11
D2
D1
D0
tsu
th
th
tw(SCLK)
005aaa065
CS
tw(SCLKL)
tw(SCLKH)


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