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ADC1215S Datasheet(PDF) 12 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 12 Page - NXP Semiconductors

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10.2 Clock and digital output timing
Table 8.
Clock and digital output timing characteristics[1]
Symbol
Parameter
Conditions
ADC1215S065
ADC1215S080
ADC1215S105
ADC1215S125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
20
-
65
60
-
80
75
-
105
100
-
125
MHz
tlat(data)
data latency
time
-
14
-
-
14
-
-
14
-
-
14
-
clocks
cycle
δ
clk
clock duty cycle
DCS_EN = 1
30
50
70
30
50
70
30
50
70
30
50
70
%
DCS_EN = 0
455055
45
50
55
455055455055%
td(s)
sampling delay
time
-0.8
--
0.8
--0.8
--0.8
-ns
twake
wake-up time
-<tbd>
--
<tbd>
--<tbd>
--<tbd>
-ns
CMOS mode timing output: pins D11 to D0 and DAV
tPD
propagation
delay
DATA
-3.9
--
3.9
--3.9
--3.9
-ns
DAV
-
4.2
-
-
4.2
--4.2
--4.2
-ns
tsu
set-up time
-7.7
--
6.5
--4.7
--4.3
-ns
th
hold time
-6.7
--
5.5
--3.8
--3.5
-ns
tr
rise time[2]
DATA
0.5-
2.40.5
-
2.4
0.5-
2.40.5
-
2.4
ns
DAV
0.5
-
2.4
0.5
-
2.4
0.5
-
2.4
0.5
-
2.4
ns
tf
fall time[2]
DATA
0.5-
2.40.5
-
2.4
0.5-
2.40.5
-
2.4
ns


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