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ADC1215S Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 1 Page - NXP Semiconductors

 
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1.
General description
The ADC1215S is a single channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1215S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
thanks to a separate digital output supply.
The ADC1215S supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1215S is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures
that the input impedance remains constant and low and the performance consistent over
a wide frequency range.
2.
Features and benefits
ADC1215S series
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
with input buffer; CMOS or LVDS DDR digital outputs
Rev. 01 — 12 April 2010
Preliminary data sheet
SNR, 70 dBFS / SFDR, 86 dBc
Input bandwidth, 600 MHz
Sample rate up to 125 Msps
Power dissipation, 635 mW at 80 Msps,
including analog input buffer
12-bit pipelined ADC core
SPI
Clock input divider by 2 for less jitter
contribution
Duty cycle stabilizer
Integrated input buffer
Fast OuT of Range (OTR) detection
Flexible input voltage range: 1 V (p-p) to
2 V (p-p)
INL
±1.25 LSB, DNL ±0.25 LSB
CMOS or LVDS DDR digital outputs
Offset binary, two’s complement, gray
code
Pin compatible with the ADC1415S
series, the ADC1015S series and the
ADC1115S125
Power-down and Sleep modes
HVQFN40 package


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