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ADC1215S Datasheet(PDF) 7 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 7 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
7 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
9.
Static characteristics
Table 6.
Static characteristics[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDA(5V)
analog supply voltage 5 V
4.75
5.0
5.25
V
VDDA(3V)
analog supply voltage 3 V
2.85
3.0
3.4
V
VDDO
output supply voltage
CMOS mode
1.65
1.8
3.6
V
LVDS DDR mode
2.85
3.0
3.6
V
IDDA(5V)
analog supply current 5 V
fclk =125 Msps;
fi =70 MHz
-46
-
mA
IDDA(3V)
analog supply current 3 V
fclk =125 Msps;
fi =70 MHz
-205
-
mA
IDDO
output supply current
CMOS mode;
fclk =125 Msps;
fi =70 MHz
-12
-
mA
LVDS DDR mode:
fclk =125 Msps;
fi =70 MHz
-39
-
mA
P
power dissipation
ADC1215S125;
analog supply only
-840
-
mW
ADC1215S105;
analog supply only
-770
-
mW
ADC1215S080;
analog supply only
-635
-
mW
ADC1215S065;
analog supply only
-580
-
mW
Power-down mode
-
2
-
mW
Standby mode
-
40
-
mW
Clock inputs: pins CLKP and CLKM
LVPECL
Vi(clk)dif
differential clock input voltage
peak-to-peak
-
±1.6
-
V
LVDS
Vi(clk)dif
differential clock input voltage
peak-to-peak
-
±0.70
-
V
SINE wave
Vi(clk)dif
differential clock input voltage
peak-to-peak
±0.8
±3.0
-
V
LVCMOS
VIL
LOW-level input voltage
-
-
0.3VDDA(3V)
V
VIH
HIGH-level input voltage
0.7VDDA(3V)
--
V
Logic inputs: pins PWD and OE
VIL
LOW-level input voltage
0
-
0.8
V
VIH
HIGH-level input voltage
2
-
VDDA(3V)
V
IIL
LOW-level input current
<tbd>
-
<tbd>
μA
IIH
HIGH-level input current
−10
-
+10
μA


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