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ADC1215S Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 5 Page - NXP Semiconductors

 
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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
5 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
D11
17
O
data output bit 11 (MSB)
D10
18
O
data output bit 10
D9
19
O
data output bit 9
D8
20
O
data output bit 8
D7
21
O
data output bit 7
D6
22
O
data output bit 6
D5
23
O
data output bit 5
D4
24
O
data output bit 4
D3
25
O
data output bit 3
D2
26
O
data output bit 2
D1
27
O
data output bit 1
D0
28
O
data output bit 0 (LSB)
n.c.
29
-
not connected
n.c.
30
-
not connected
DAV
31
O
data valid output clock
n.c.
32
-
not connected
VDDO
33
P
output power supply
OGND
34
G
output ground
OTR
35
O
out of range
SCLK/DFS
36
I
SPI clock / data format select
SDIO/ODS
37
I/O
SPI data IO / output data standard
CS
38
I
SPI chip select
SENSE
39
I
reference programming pin
VREF
40
I/O
voltage reference input/output
Table 3.
Pin description (LVDS/DDR) digital outputs)
Symbol
Pin [1]
Type [2]
Description
D10_D11_M
17
O
differential output data D10 and D11 multiplexed, complement
D10_D11_P
18
O
differential output data D10 and D11 multiplexed, true
D8_D9_M
19
O
differential output data D8 and D9 multiplexed, complement
D8_D9_P
20
O
differential output data D8 and D9 multiplexed, true
D6_D7_M
21
O
differential output data D6 and D7 multiplexed, complement
D6_D7_P
22
O
differential output data D6 and D7 multiplexed, true
D4_D5_M
23
O
differential output data D4 and D5 multiplexed, complement
D4_D5_P
24
O
differential output data D4 and D5 multiplexed, true
D2_D3_M
25
O
differential output data D2 and D3 multiplexed, complement
D2_D3_P
26
O
differential output data D2 and D3 multiplexed, true
D0_D1_M
27
O
differential output data D0 and D1 multiplexed, complement
D0_D1_P
28
O
differential output data D0 and D1 multiplexed, true
n.c.
29
-
not connected
Table 2.
Pin description (CMOS digital outputs)
Symbol
Pin
Type [1]
Description


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