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ADC1215S Datasheet(PDF) 31 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 31 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
31 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Table 21.
Internal reference control register (address 0008h) bit description
Bit
Symbol
Access
Value
Description
7 to 4
-
0000
not used
3
INTREF_EN
R/W
programmable internal reference enable
0
disable
1
active
2 to 0
INTREF[2:0]
R/W
programmable internal reference
000
0dB (FS=2V)
001
−1dB (FS=1.78 V)
010
−2dB (FS=1.59 V)
011
−3dB (FS=1.42 V)
100
−4dB (FS=1.26 V)
101
−5dB (FS=1.12 V)
110
−6dB (FS=1V)
111
reserved
Table 22.
Input buffer control register (address 0010h) bit description
Bit
Symbol
Access
Value
Description
7 to 2
-
000000
not used
1 to 0
IB_IBIAS[1:0]
R/W
input buffer bias current
00
not used
01
medium
10
low
11
high
Table 23.
Output data standard control register (address 0011h) bit description
Bit
Symbol
Access
Value
Description
7 to 5
-
000
not used
4
LVDS_CMOS
R/W
output data standard: LVDS DDR or CMOS
0
CMOS
1
LVDS DDR
3
OUTBUF
R/W
output buffers enable
0
output enabled
1
output disabled (high Z)
2
OUTBUS_SWAP
R/W
output bus swapping
0
no swapping
1
output bus is swapped (MSB becomes LSB and vice versa)
1 to 0
DATA_FORMAT[1:0]
R/W
output data format
00
offset binary
01
two’s complement
10
gray code
11
offset binary


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