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ADC1215S Datasheet(PDF) 30 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 30 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
30 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Table 19.
Reset and operating mode control register (address 0005h) bit description
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
reset digital section
0
no reset
1
performs a reset on SPI registers
6 to 4
RESERVED[2:0]
000
reserved
3 to 2
-
00
not used
1 to 0
OP_MODE[1:0]
R/W
operating mode
00
normal (Power-up)
01
Power-down
10
Sleep
11
normal (Power-up)
Table 20.
Clock control register (address 0006h) bit description
Bit
Symbol
Access
Value
Description
7 to 5
-
000
not used
4
SE_SEL
R/W
single-ended clock input pin select
0
CLKM
1CLKP
3
DIFF_SE
R/W
differential/single ended clock input select
0
fully differential
1
single-ended
2
-
0
not used
1
CLKDIV
R/W
clock input divide by 2
0
disabled
1
enabled
0
DCS_EN
R/W
duty cycle stabilizer
0
disabled
1
enabled


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