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ADC1215S Datasheet(PDF) 28 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 28 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
28 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 24. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
CS
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
Offset binary, LVDS DDR
default mode at start-up
005aaa063
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
two's complement, CMOS
default mode at start-up
005aaa064
CS


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