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ADC1215S Datasheet(PDF) 27 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 27 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
27 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but will always
be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end on data transmission.
11.6.2 Default modes at start-up
During circuit initialization, it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS will trigger a transition to SPI control mode. When the ADC1215S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 23). Once in SPI control mode, the output data standard
can be changed via bit LVDS/CMOS in Table 23.
When the ADC1215S enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] in Table 23.
Table 17.
Number of data bytes to be transferred after the instruction bytes
W1
W0
Number of bytes transmitted
00
1 byte
01
2 bytes
10
3 bytes
1
1
4 bytes or more
Fig 22. SPI mode timing
SCLK
SDIO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D3
D2
D1
D0
D0
D7
D6
D5
D4
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa062
CS


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