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ADC1215S Datasheet(PDF) 24 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 24 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
24 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see Table 23).
Each output should be terminated externally with a 100
Ω resistor (typical) at the receiver
side (Figure 20) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 21 and
Table 32).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic
voltage levels.
Fig 20. LVDS DDR digital output buffer - externally terminated
Fig 21. LVDS DDR digital output buffer - internally terminated
Table 13.
LVDS DDR output register 2
LVDS_INT_TER[2:0]
Resistor value (
Ω)
000
no internal termination
001
300
010
180
011
110
100
150
VCCO
3.5 mA
typ
DnP/Dn + 1P
DnM/Dn + 1M
OGND
100
Ω
005aaa058
+
+
RECEIVER
VCCO
OGND
005aaa059
DxP/Dx + 1P
DxM/Dx + 1M
100
Ω
3.5 mA
typ
+
+
RECEIVER


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