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ADC1215S Datasheet(PDF) 21 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 21 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
21 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input
buffer bias current can be set to one of three levels (high, medium or low) via the SPI
(see Table 22).
11.4 Clock input
11.4.1 Drive modes
The ADC1215S can be driven differentially (SINE, LVPECL or LVDS) with little or no
degradation on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or
CLKM (CLKP should be connected to ground via a capacitor).
a. Rising edge LVCMOS
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
a. Sine clock input
b. Sine clock input (with transformer)
c. LVDS clock input
d. LVPECL clock input
Fig 17. Differential clock input
LVCMOS
clock input
CLKP
CLKM
005aaa174
005aaa053
LVCMOS
clock input
CLKP
CLKM
Sine
clock input
CLKP
CLKM
005aaa173
Sine
clock input
CLKP
CLKM
005aaa054
005aaa055
LVDS
clock input
CLKP
CLKM
LVPECL
clock input
005aaa172
CLKP
CLKM


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