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ADC1215S Datasheet(PDF) 20 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 20 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
20 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
Figure 12 to Figure 15 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
11.3.2 Reference gain control
The reference gain is programmable between 0 dB to
−6 dB in 1 dB steps via the SPI (see
Table 21). The corresponding full-scale input voltage range varies between 2 V (p-p) and
1 V (p-p), as shown in Table 12:
11.3.3 Common-mode output voltage (VO(cm))
A 0.1
μF filter capacitor should be connected between pin VCM and ground.
Fig 12. Internal reference, 2 V (p-p) full-scale
Fig 13. Internal reference, 1 V (p-p) full-scale
Fig 14. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 15. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
330 pF
VREF
SENSE
005aaa116
REFERENCE
EQUIVALENT
SCHEMATIC
330
pF
005aaa117
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
0.1
μF
VDDA
V
005aaa119
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
330 pF
005aaa118
VREF
SENSE
Table 12.
Reference SPI Gain Control
INTREF
Gain
full scale (p-p)
000
0 dB
2 V
001
−1dB
1.78 V
010
−2dB
1.59 V
011
−3dB
1.42 V
100
−4dB
1.26 V
101
−5dB
1.12 V
110
−6dB
1 V
111
reserved
x


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