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ADC1215S Datasheet(PDF) 18 Page - NXP Semiconductors

Part No. ADC1215S
Description  Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1215S Datasheet(HTML) 18 Page - NXP Semiconductors

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ADC1215S_SER_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
18 of 39
NXP Semiconductors
ADC1215S series
ADC1215S series; input buffer; CMOS or LVDS DDR digital output
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 9 would be suitable for a baseband application.
The configuration shown in Figure 10 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
Fig 9.
Single transformer configuration suitable for baseband applications
Fig 10. Dual transformer configuration suitable for high intermediate frequency
application
005aaa108
100 nF
100 nF
100 nF
100 nF
INP
INM
VCM
Analog
input
ADT1-1WT
100 nF
100 nF
50
Ω
005aaa109
100 nF
100 nF
100 nF
INP
INM
100
Ω
50
Ω
50
Ω
ADT1-1WT
ADT1-1WT
Analog
input
100 nF
100 nF
VCM
100 nF


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