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ADC1115S125 Datasheet(PDF) 35 Page - NXP Semiconductors |
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ADC1115S125 Datasheet(HTML) 35 Page - NXP Semiconductors |
35 / 35 page NXP Semiconductors ADC1115S125 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 April 2010 Document identifier: ADC1115S125_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 Static characteristics . . . . . . . . . . . . . . . . . . . . . 5 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.2 Clock and digital output timing . . . . . . . . . . . . . 9 10.3 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 Application information. . . . . . . . . . . . . . . . . . 11 11.1 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 11 11.1.1 SPI and Pin control modes . . . . . . . . . . . . . . . 11 11.1.2 Operating mode selection. . . . . . . . . . . . . . . . 12 11.1.3 Selecting the output data standard . . . . . . . . . 12 11.1.4 Selecting the output data format. . . . . . . . . . . 12 11.2 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12 11.2.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 11.2.2 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 14 11.3 System reference and power management . . 15 11.3.1 Internal/external references . . . . . . . . . . . . . . 15 11.3.2 Reference gain control . . . . . . . . . . . . . . . . . . 16 11.3.3 Common-mode output voltage (VO(cm)) . . . . . 16 11.3.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.4.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.4.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 18 11.4.3 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 18 11.4.4 Clock input divider . . . . . . . . . . . . . . . . . . . . . 18 11.5 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.5.1 Digital output buffers: CMOS mode . . . . . . . . 19 11.5.2 Digital output buffers: LVDS DDR mode . . . . . 20 11.5.3 Data valid (DAV) output clock . . . . . . . . . . . . . 21 11.5.4 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 21 11.5.5 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.5.6 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.5.7 Output codes versus input voltage . . . . . . . . . 22 11.6 Serial Peripheral Interface (SPI) . . . . . . . . . . . 22 11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 22 11.6.2 Default modes at start-up . . . . . . . . . . . . . . . . 23 11.6.3 Register allocation map . . . . . . . . . . . . . . . . . 25 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 31 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32 14 Legal information . . . . . . . . . . . . . . . . . . . . . . 33 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33 14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15 Contact information . . . . . . . . . . . . . . . . . . . . 34 16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 |
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