ADC1115S125 datasheet(26/35 Pages) NXP

Part #	ADC1115S125

Description	Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

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Manufacturer	NXP [NXP Semiconductors]

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ADC1115S125_1

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Preliminary data sheet

Rev. 01 — 12 April 2010

26 of 35

NXP Semiconductors

ADC1115S125

11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 19.

Reset and operating mode control register (address 0005h) bit description

Bit

Symbol

Access

Value

Description

7

SW_RST

R/W

reset digital section

0

no reset

1

performs a reset on SPI registers

6 to 4

RESERVED[2:0]

000

reserved

3 to 2

-

00

not used

1 to 0

OP_MODE[1:0]

R/W

operating mode

00

normal (Power-up)

01

Power-down

10

Sleep

11

normal (Power-up)

Table 20.

Clock control register (address 0006h) bit description

Bit

Symbol

Access

Value

Description

7 to 5

-

000

not used

4

SE_SEL

R/W

single-ended clock input pin select

0

CLKM

1CLKP

3

DIFF_SE

R/W

differential/single ended clock input select

0

fully differential

1

single-ended

2

-

0

not used

1

CLKDIV

R/W

clock input divide by 2

0

disabled

1

enabled

0

DCS_EN

R/W

duty cycle stabilizer

0

disabled

1

enabled

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ADC1115S125 Datasheet(PDF) 26 Page - NXP Semiconductors

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