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ADC1005S060 Datasheet(PDF) 8 Page - NXP Semiconductors

Part No. ADC1005S060
Description  Single 10 bits ADC, up to 60 MHz
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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ADC1005S060 Datasheet(HTML) 8 Page - NXP Semiconductors

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ADC1005S060_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 August 2008
8 of 19
NXP Semiconductors
ADC1005S060
Single 10 bits ADC, up to 60 MHz
Eoffset
offset error
middle code
-
±1
-
LSB
EG
gain error
from device to device
[5] -
±0.5
-
%
Bandwidth
B
bandwidth
full-scale sine wave
[6] -
30
-
MHz
75 % full-scale sine wave
-
45
-
MHz
small signal at mid-scale;
VI = ±10 LSB at code 512
-
700
-
MHz
ts(LH)
LOW to HIGH
settling time
full-scale square wave;
see Figure 6
[7] -5
-ns
ts(HL)
HIGH to LOW
settling time
full-scale square wave;
see Figure 6
[7] -5
-ns
Harmonics
α2H
second harmonic
level
fi = 5 MHz
-
−68
-
dB
α3H
third harmonic
level
fi = 5 MHz
-
−67
-
dB
THD
total harmonic
distortion
fi = 5 MHz
-
−64
-
dB
fi = 15 MHz
-
−57
-
dB
SFDR
spurious free
dynamic range
fi = 5 MHz
-
72
dB
Signal-to-Noise ratio[8]
S/N
signal-to-noise
ratio
without harmonics;
fi = 5 MHz
-58
-
dB
without harmonics;
fi =15MHz
53
57
-
dB
Effective bits[8]
ENOB
effective number
of bits
fi = 5 MHz
-
9.3
-
bits
fi = 10 MHz
-
8.9
-
bits
fi = 15 MHz
-
8.8
-
bits
fi = 20 MHz
-
8.6
-
bits
Two-tone intermodulation[9]
αIM
intermodulation
suppression
fclk = 60 MHz
-
−67
-
dB
Bit error rate
BER
bit error rate
fi = 5 MHz; VI = ±16 LSB at
code 512
-10−13
-
times/samples
Timing (fclk = 60 MHz; CL = 10 pF); see Figure 4[10]
td(s)
sampling delay
time
-
0.7
2
ns
th(o)
output hold time
4
-
-
ns
td(o)
output delay time
VCCO = 2.7 V
-
10
14
ns
VCCO = 3.3 V
-
9
13
ns
Table 6.
Characteristics …continued
VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; AGND and DGND shorted together; Tamb =0 °Cto70 °C; typical values
measured at VCCA = VCCD = 5 V; VCCO = 3.3 V; VRB = 1.3 V; VRT = 3.7 V; CL = 10 pF and Tamb =25 °C unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit


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