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74LVC3GU04GM Datasheet(PDF) 1 Page - NXP Semiconductors |
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74LVC3GU04GM Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 17 page 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. 2. Features I Wide supply voltage range from 1.65 V to 5.5 V I 5 V tolerant input/output for interfacing with 5 V logic I High noise immunity I Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8B/JESD36 (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I ±24 mA output drive at VCC = 3.0 V I CMOS low power consumption I Latch-up performance exceeds 250 mA I Multiple package options I Specified from −40 °Cto+85 °C and from −40 °C to +125 °C. 3. Ordering information 74LVC3GU04 Triple inverter Rev. 07 — 11 November 2009 Product data sheet Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC3GU04DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC3GU04DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 |
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