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74LVC1G175 Datasheet(PDF) 9 Page - NXP Semiconductors

Part No. 74LVC1G175
Description  Single D-type flip-flop with reset; positive-edge trigger
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Maker  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LVC1G175 Datasheet(HTML) 9 Page - NXP Semiconductors

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74LVC1G175_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 21 May 2007
9 of 17
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
12. Waveforms
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7.
The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to
D hold times, and the maximum clock pulse frequency
001aaa465
th
tsu
th
tPHL
tW
tPLH
tsu
1/fmax
VM
VM
VM
VI
GND
VI
GND
CP input
D input
VOH
VOL
Q output
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 8.
The master reset (MR) input to output (Q) propagation delays, the master reset pulse width, and the MR to
CP recovery time
001aaa464
MR input
CP input
Q output
tPHL
tW
trec
VM
VI
GND
VI
VOH
VOL
GND
VM
VM


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