EN

1

24

FSW

2

NC

4

GND

5

PWMIN

6

7

8

9

10

11

12

13

14

15

16

17

18

23

22

21

20

19

IFB3

IFB2

IFB1

OVP

PGND 2

PGND 1

TPS61185

TPS61185

www.ti.com

SLVSAA1A – APRIL 2010 – REVISED MAY 2010

DEVICE INFORMATION

24 PIN RGE PACKAGE

TOP VIEW

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NAME

NO.

EN

1

I

Device enable pin.

FSW

2

I

Switching frequency program pin. Use a resistor from this pin to GND to set the boost switch frequency

from 600 kHz to 2 MHz.

FPWMO

3

O

Dimming frequency program pin. When the mode pin is open or pulled high, the resistor on this pin to GND

programs the PWM dimming frequency between 100 Hz to 5 kHz.

NC

4

I

No connection pin.

GND

5

I

Signal ground of the IC. Tie the ground of noise sensitive components to GND.

PWMIN

6

I

Dimming control logic input. The dimming frequency range is 100 Hz to 20 kHz.

IFB8-IFB5

7–10

O

Current sink regulation inputs. They are connected to the cathode of the WLEDs. Connect any unused IFB

IFB4-IFB1

12–15

25 mA current.

ISET

11

O

The resistor on this pin programs WLED output current. Tie resistor ground to GND.

OVP

16

I

Over voltage programming pin. The OVP voltage threshold is set through an external resistor divider

combination according to equation 4.

PGND2

17

I

Power grounds of the IC. Internally connect to the source of the PWM switch. Tie the ground of power

stage components to these grounds.

PGND1

18

I

SW2

19

I

Drain connections of the internal PWM switch MOSFET and external Schottky diode.

SW1

20

I

FAULT

21

O

Gate driver output for an external PFET used for fault protection. It can also be used as signal output for

system fault report.

MODE

22

I

Dimming mode select pin. When MODE is high or open, the internal dimming frequency is programmable

by a resistor on pin 3 (FPWMO pin); when MODE is low, the internal dimming frequency is the same as the

PWM input signal on pin 6 (PWMIN pin).

23

I

This pin is connected to the battery supply. It also provides the pull-up voltage for the FAULT pin.

VDD

24

O

The supply rail of internal logic. Connect a 1-µF capacitor from VDD to GND.

Copyright © 2010, Texas Instruments Incorporated

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Product Folder Link(s): TPS61185