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TPS63010 Datasheet(PDF) 22 Page - Texas Instruments |
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TPS63010 Datasheet(HTML) 22 Page - Texas Instruments |
22 / 28 page THERMAL INFORMATION P D(MAX) + T J(MAX) * T A R q JA + 125°C * 85°C 84 °C W + 476 mW (7) PACKAGE INFORMATION Package Dimensions TPS63010 TPS63011 TPS63012 SLVS653A – JUNE 2008 – REVISED AUGUST 2009 ........................................................................................................................................................ www.ti.com Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below. 1. Improving the power dissipation capability of the PCB design 2. Improving the thermal coupling of the component to the PCB by soldering all pins to traces as wide as possible. 3. Introducing airflow in the system The maximum recommended junction temperature (TJ) of the TPS6301x devices is 125°C. The thermal resistance of this 20-pin chipscale package (YFF) is RθJA = 84°C/W, if all pins are soldered. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 476 mW, as calculated in Equation 7. More power can be dissipated if the maximum ambient temperature of the application is lower. The package dimensions for this YFF package are shown in the table below. See the package drawing at the end of this data sheet for more details. YFF Package Dimensions Packaged Devices D E TPS63010YFF 2.14 ± 0.05 mm 1.93 ± 0.05 mm 22 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS63010 TPS63011 TPS63012 |
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Similar Description - TPS63010_09 |
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