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ISO3082DWRG4 Datasheet(PDF) 10 Page - Texas Instruments |
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ISO3082DWRG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 19 page ISO3080, ISO3086 ISO3082, ISO3088 SLOS581C – MAY 2008 – REVISED OCTOBER 2009 www.ti.com REGULATORY INFORMATION VDE CSA UL Approved under CSA Component Recognized under 1577 Component Certified according to IEC 60747-5-2 Acceptance Notice Recognition Program(1) File Number: 40016131 File Number: 1698195 File Number: E181974 (1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577. IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER MIN TYP MAX UNIT Safety input, output, or supply θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, IS DW-16 210 mA current TA = 25°C TS Maximum case temperature DW-16 150 °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-K Thermal Resistance(1) 168 θJA Junction-to-Air °C/W High-K Thermal Resistance 96.1 θJB Junction-to-Board Thermal Resistance 61 °C/W θJC Junction-to-Case Thermal Resistance 48 °C/W VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF, PD Device Power Dissipation 220 mW Input a 20 MHz 50% duty cycle square wave (1) Tested in accordance with the Low-K or High-K thermal metric defintions of EIA/JESD51-3 for leaded surface mount packages. 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ISO3080, ISO3086 ISO3082, ISO3088 |
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