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AM3517BZCN Datasheet(PDF) 2 Page - Texas Instruments |
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AM3517BZCN Datasheet(HTML) 2 Page - Texas Instruments |
2 / 218 page AM3517, AM3505 SPRS550A – OCTOBER 2009 – REVISED MAY 2010 www.ti.com Compensation – ARM Instructions - Little Endian – 10-bit to 8-bit A-law Compression Hardware – ARM Data – Configurable – Supports up to 16K Pixels (Image Size) in • SDRC Memory Controller Horizontal and Vertical Directions – 16/32-bit Memory Controller With 1G-Byte • System Direct Memory Access (sDMA) Total Address Space Controller (32 Logical Channels With – Double Data Rate (DDR2) SDRAM, mobile Configurable Priority) Double Data Rate (mDDR)SDRAM • Comprehensive Power, Reset and Clock – SDRAM Memory Scheduler (SMS) and Management Rotation Engine • ARM CortexTM-A8 Memory Architecture • General Purpose Memory Controller (GPMC) – ARMv7 Architecture – 16-bit Wide Multiplexed Address/Data Bus • Trust Zone – Up to 8 Chip Select Pins With 128M-Byte • Thumb-2 Address Space per Chip Select Pin • MMU Enhancements – Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code – In-Order, Dual-Issue, Superscalar Calculation), SRAM and Pseudo-SRAM Microprocessor Core – Flexible Asynchronous Protocol Control for – NEON Multimedia Architecture Interface to Custom Logic (FPGA, CPLD, – Over 2x Performance of ARMv6 SIMD ASICs, etc.) – Supports Both Integer and Floating Point – Nonmultiplexed Address/Data Mode (Limited SIMD 2K-Byte Address Space) – JAZELLE RCT Execution Environment • Test Interfaces Architecture – IEEE-1149.1 (JTAG) Boundary-Scan – Dynamic Branch Prediction with Branch Compatible Target Address Cache, Global history buffer – Embedded Trace Macro Interface (ETM) and 8 entry return stack • 65-nm CMOS technology – Embedded Trace Macrocell [ETM] support for Non_invasive Debug • Packages: – 16K-Byte instruction Cache (4-Way set- – 491-pin BGA (17x17, 0.65mm pitch) associative) [ZCN suffix] with via channel array technology – 16K-Byte Data Cache (4-Way Set-Associative) – 484-pin PBGA (23x23, 1mm pitch) [ZER suffix] – 256K-Byte L2 Cache • Applications: • POWERVR SGX™ Graphics Accelerator – Single Board Computers – Tile Based Architecture Delivering up to 10 MPoly/sec – Industrial and Home Automation – Universal Scalable Shader Engine: – Digital Signage Multi-threaded Engine Incorporating Pixel – Point of Service and Vertex Shader Functionality – Portable Media Player – Industry Standard API Support: OpenGLES – Portable Industrial 1.1 and 2.0, OpenVG1.0 – Transportation – Fine Grained Task Switching, Load – Navigation Balancing, and Power Management – Smart White Goods – Programmable, High-Quality Image – Digital TV Anti-Aliasing – Digital Video Camera • Endianess – Gaming 2 AM3517/05 ARM Microprocessor Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 |
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