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ADS7924 Datasheet(PDF) 5 Page - Texas Instruments |
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ADS7924 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 42 page SCL SDA t R t HDSTA t HDSTA t HDDAT t BUF t HIGH t SUSTA t SUSTO P S Sr P t SP t VDACK t SUDAT 9thClock t VDDAT t F t LOW ADS7924 www.ti.com SBAS482A – JANUARY 2010 – REVISED MAY 2010 TIMING DIAGRAM NOTE: S = Start, Sr = Repeated Start, and P = Stop. Figure 1. I2C Timing Diagram Table 1. I2C Timing Definitions ADS7924 PARAMETER MIN MAX UNIT SCL operating frequency fSCL 0 0.4 MHz Bus free time between START and STOP condition tBUF 1.3 ms Hold time after repeated START condition. tHDSTA 600 ns After this period, the first clock is generated. Repeated START condition setup time tSUSTA 600 ns Stop condition setup time tSUSTO 600 ns Data hold time tHDDAT 0 ns Data setup time tSUDAT 100 ns SCL clock low period tLOW 1300 ns SCL clock high period tHIGH 600 ns Clock/data fall time tF 300 ns Clock/data rise time tR 300 ns Data valid time tVDDAT 0.9 ms Data valid acknowledge time tVDACK 0.9 ms Pulse width of spike that must be suppressed by the input filter tSP 0 50 ns Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): ADS7924 |
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