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74HCT4060D Datasheet(PDF) 12 Page - NXP Semiconductors |
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74HCT4060D Datasheet(HTML) 12 Page - NXP Semiconductors |
12 / 25 page ![]() 74HC_HCT4060_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 July 2008 12 of 25 NXP Semiconductors 74HC4060; 74HCT4060 14-stage binary ripple counter with oscillator [1] tpd is the same as tPHL and tPLH. [2] Qn+1 is the next Qn output. [3] tt is the same as tTHL and tTLH. [4] CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(C L × VCC 2 × f o) = sum of outputs. 12. Waveforms CPD power dissipation capacitance VI = GND to VCC − 1.5 V; VCC =5V; fi = 1 MHz [4] -40 - - - - - pF Table 6. Dynamic characteristics …continued GND = 0 V; CL = 50 pF unless otherwise specified; for test circuit see Figure 11. Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max Measurement points are given in Table 7. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Waveforms showing the clock (RS) to output (Q3) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency 001aai118 RS input 1/fmax tW tTHL tTLH tPHL tPLH VOH VI GND VOL VM VM 10 % 90 % 90 % 10 % Q3 output |
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